1. Field of the Invention
The present invention relates to an electronic device package, and in particular relates to an isolation layer of an electronic device package and a method for fabricating an electronic device package using a wafer scale package (WSP) process.
2. Description of the Related Art
In the conventional electronic device packages, the surroundings of the chip are usually encapsulated by an isolation layer, thereby isolating the chip from a subsequently formed conductive wiring layer. The conventional isolation layer has good resolution to facilitate openings forming therein so that a subsequently formed conductive wiring layer electrically connects to the chip. The conventional isolation layer with good resolution, however, is usually thin, thereby not being able to compatibly satisfy surface flatness, mechanical strength and coefficient thermal expansion (CTE) requirements. Contrarily, an isolation layer compatibly satisfying surface flatness, mechanical strength and coefficient thermal expansion (CTE) requirements must be thick, thereby not being able to satisfy good resolution requirements.
Thus, a novel electronic device package and a method for fabricating the same are desired to satisfy all the aforementioned requirements.